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2. Modify the below VHDL code (four-bit up-counter) by adding a parameter that sets the number of flip-flops in the counter. LIBRARY leee; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD_LOGIC : Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn) BEGIN IF Resetn = ' 0 ' THEN Count