2. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? a. Because...
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2. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? a. Because of inverted outputs b. Because of triggering functionality c. Because of cross-coupled connection d. Because of inverted outputs & triggering functionality 3. Whose operations are faster among the following? a. Combinational circuits b. Sequential circuits c. Latches d. Flip-flops 4. What is an indeterminate condition in a NAND based S'-R' latch? a. S'-0, R-1 b. S'-1, R-0 c. S'-1, R-1 d. S'-0, R-0 5. The S-R flip flop consist of a. 4 AND gates b. Two additional AND gates c. An additional clock input d. 3 AND gates 6. What is one disadvantage of an S-R flip-flop? a. It has no Enable input b. It has a RACE condition c. It has no clock input d. Invalid State 7. Which of the following is correct for a gated D-type flip-flop? a. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b. The output complement follows the input when enabled c. Only one of the inputs can be HIGH at a time d. The output toggles if one of the inputs is held HIGH 2. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? a. Because of inverted outputs b. Because of triggering functionality c. Because of cross-coupled connection d. Because of inverted outputs & triggering functionality 3. Whose operations are faster among the following? a. Combinational circuits b. Sequential circuits c. Latches d. Flip-flops 4. What is an indeterminate condition in a NAND based S'-R' latch? a. S'-0, R-1 b. S'-1, R-0 c. S'-1, R-1 d. S'-0, R-0 5. The S-R flip flop consist of a. 4 AND gates b. Two additional AND gates c. An additional clock input d. 3 AND gates 6. What is one disadvantage of an S-R flip-flop? a. It has no Enable input b. It has a RACE condition c. It has no clock input d. Invalid State 7. Which of the following is correct for a gated D-type flip-flop? a. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b. The output complement follows the input when enabled c. Only one of the inputs can be HIGH at a time d. The output toggles if one of the inputs is held HIGH
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Answer 2 c Because of crosscoupled connection The crosscoupled connections from the output of one ga... View the full answer
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Financial Markets and Institutions
ISBN: 978-0077861667
6th edition
Authors: Anthony Saunders , Marcia Cornett
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