[25 pts] 2- Consider the implementation of the sTD Y+q, Rr (Store Indirect with Displacement) instruction on the enhanced AVR datapath (a) List and explain the sequence of microoperations required to implement STD Ytq, Rr. Note that this instruction takes two execute cycles (EXI and EX2) (b) List and explain the control signals and the Register Address Logic (RAL) output for the STD Y+q, Rr nstruction. Control signals for the Fetch cycle are given below. Clearly explain your reasoning STD Y+q, Rr EX1 Control Signals MJ MK ML R en PC en PCh en PCl en NPC en SP en DEMUX MA MB ALU f MC RF wA RF wB MD ME DM r DM w MF MG Adder f Inc Dec MH MI IF EX2 EX1 EX2 Output WA WB [25 pts] 2- Consider the implementation of the sTD Y+q, Rr (Store Indirect with Displacement) instruction on the enhanced AVR datapath (a) List and explain the sequence of microoperations required to implement STD Ytq, Rr. Note that this instruction takes two execute cycles (EXI and EX2) (b) List and explain the control signals and the Register Address Logic (RAL) output for the STD Y+q, Rr nstruction. Control signals for the Fetch cycle are given below. Clearly explain your reasoning STD Y+q, Rr EX1 Control Signals MJ MK ML R en PC en PCh en PCl en NPC en SP en DEMUX MA MB ALU f MC RF wA RF wB MD ME DM r DM w MF MG Adder f Inc Dec MH MI IF EX2 EX1 EX2 Output WA WB