Question: 27. Write a VHDL design for a D Flip-Flop with asynchronous reset. The DFF should include an activehigh RESET input and a QN output. Implement

27. Write a VHDL design for a D Flip-Flop with asynchronous

27. Write a VHDL design for a D Flip-Flop with asynchronous reset. The DFF should include an activehigh RESET input and a QN output. Implement a 32-bit register using the D Flip-Flop. The register should include an active-high EN input. Implement a 3232 RAM using the register. Write a testbench for each module

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