Question: 2-bit counter design and simulation. a) Write a VHDL module for the 2 bit counter (with active high reset signal) using two JK flip-flops. b)

2-bit counter design and simulation. a) Write a VHDL module for

2-bit counter design and simulation. a) Write a VHDL module for the 2 bit counter (with active high reset signal) using two JK flip-flops. b) Write a Verilog testbench module for the counter and perform the simulation

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1. Who is responsible for resolving this dilemma?

3. What is at stake for you? What are your values? Are there motives that may be persuading you in one direction instead of another?

7. How might you go about testing these assumptions?