3. [5 points] Assume that some I/O device has the maximum data transfer rate of R1/o 4 MB/s. During DMA, the data is transferred in blocks of dI/0-DMA-4 KB at a time. To initiate a DMA transfer, the CPU takes NDMA-start-1,600 clock cycles, to complete it, the CPU takes NDMA-end-800 clock cycles. If polling is used, the data is transferred in blocks of d/o 32 B at a time, when the device is ready. To perform a poll, the CPU takes either Npoll-ready 800 clock cycles (when the device is ready), or Npoll-not-ready - 400 clock cycles (when the device is not ready). At what activity percentage of the I/O device does the DMA cost become 400 times cheaper than the polling cost? 3. [5 points] Assume that some I/O device has the maximum data transfer rate of R1/o 4 MB/s. During DMA, the data is transferred in blocks of dI/0-DMA-4 KB at a time. To initiate a DMA transfer, the CPU takes NDMA-start-1,600 clock cycles, to complete it, the CPU takes NDMA-end-800 clock cycles. If polling is used, the data is transferred in blocks of d/o 32 B at a time, when the device is ready. To perform a poll, the CPU takes either Npoll-ready 800 clock cycles (when the device is ready), or Npoll-not-ready - 400 clock cycles (when the device is not ready). At what activity percentage of the I/O device does the DMA cost become 400 times cheaper than the polling cost