X=3

Y=2

Z=2

Question 3 (a) (b) A 32-bit microprocessor is designed with 32-bit instructions composing of two fields: an opcode and a 3-byte immediate operand or an operand address. The engineer would like to consider a design with either 32-bit address bus or 16-bit address bus. Justify which of the two different address bus configurations results in better performance by determining the maximum addressable memory capacity and address transfer speed. (8 marks) Consider an L1 cache with an access time of 1 ns and a hit ratio of H = 0.8YZ. The system engineer wishes to change the cache design (size of cache, cache organization) to improve H to 0.9YZ, but increase access time to 2 ns. Evaluate the conditions of the cache configuration that must be met for this change to results in improved performance. (7 marks) Consider a system in which bus cycles takes 5 YZ ns. Transfer of bus control in either direction, from processor to 1/0 device or vice versa, takes half a bus cycle. One of the I/O devices has a data transfer rate of 5X KB/s and employs DMA. Data is transferred one byte at a time. The system engineer is considering a DMA configuration in either "burst mode" (where the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred), or in "cycle-stealing mode" (at a transfer rate of 1-byte per cycle). Evaluate the performance difference between the 2 modes using a sample data block of 128 bytes, in terms of the transfer time. (10 marks) (c)