3. Considering a 8-way set associative cache for a MIPS processor, (a) If the cache contains 1284-word blocks, how many number of sets in the cache? (496) (b) How many bits are used for the tag field? How many bits are used for the cache index? (8%) (c) What is the size of the whole cache memory? Please also specify clearly how you derive the results. (For example: 8 entries x 12 bits/entry-96 bits) (8%) (d) Please draw the block diagram of the cache such as the figure on page 45 of the slide. (10%)