3. The figure attachedl shows cache memory with four-way set associative mapping. Numbers in the parentheses indicate the number of bits for each field. Note that a word is 32 bits and the cache is byte-addressable 1 Using the circled numbers, explain how you would determine cache hits misses and find data upon cache hits. 2. Find in bytes block size sct SiZC cache bank size cache size " main memory size 3. The cache is initially empty. No CPU generates the following sequence of a he addresses in H X A A 3A2. 7 ??. ? ?? ??? 7 A4.4A1 5A1 CA2. 3A1.BBB. 4B5 5B4. 6B3. SB3. 5B5.4B5 BBC. ABB. CBC. s Sh ths tan valr orc opodn each reference Use LRU (Least Recently epolicy for block replacement LRU repleshe ethat was u with the new an 6. Find the number of cache misses including compulsory misses. 7. Find the number of cache hits. 3. The figure attachedl shows cache memory with four-way set associative mapping. Numbers in the parentheses indicate the number of bits for each field. Note that a word is 32 bits and the cache is byte-addressable 1 Using the circled numbers, explain how you would determine cache hits misses and find data upon cache hits. 2. Find in bytes block size sct SiZC cache bank size cache size " main memory size 3. The cache is initially empty. No CPU generates the following sequence of a he addresses in H X A A 3A2. 7 ??. ? ?? ??? 7 A4.4A1 5A1 CA2. 3A1.BBB. 4B5 5B4. 6B3. SB3. 5B5.4B5 BBC. ABB. CBC. s Sh ths tan valr orc opodn each reference Use LRU (Least Recently epolicy for block replacement LRU repleshe ethat was u with the new an 6. Find the number of cache misses including compulsory misses. 7. Find the number of cache hits