A computer system has a 2048-byte cache. It uses fourway set associative mapping with 32 bytes in each block. The physical address size is 32 bits, and the smallest addressable unit is 1 byte.

- Draw a diagram showing the organization of the cache and indicate how physical addresses are related to the cache addresses. Clearly indicate the number of bits that are allocated to each field of the memory address.

- To what block frames of the cache can the hexadecimal address 000010AF be assigned.

- If the addresses 000010AF and FFFF7xy5 can be simultaneously assigned to the same cache set, what values can the address digits x and y have? Note that x and y are hexadecimal digits.

- If the miss rate is 11.3%, the clock cycle time is 20 nanoseconds, and the miss penalty is 200 nanoseconds, compute the average access time. Assume that the hit time is 2 clock cycles.