3) Write a Verilog module called Sat8bit. It is to implement an eight-bit saturating up counter with enable and reset. o Inputs are clock, reset and enable Output is the counter's value, Q[7:0]. The counter should set its value to 0 if reset is asserted on the positive edge of clock. If reset is a 0 and enable is a 1 it is to increment its value on the rising edge the clock. Otherwise the register should hold its value. You will be graded for correctness, syntax, and efficiency of your design and code. [9 points]