3A. For the circuit shown below, complete the truth table. 5 RO !S !R Qcurr Qnew 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3B. Draw a finite state machine (FSM) to simulate/model the sequential circuit in part A of this question. Clearly indicate the start state, transition edges, and input/output labels. Hint: Refer to the slide 88 in Lecture3.pdf () where we modeled the SR-latch as a FSM. This problem could use the same approach