(4) [14 pts) The following MIPS code is executed on a 5-stage pipelined processor with full forwarding lw $t1, -12 ($+3) LOOP: addi $t1, $t1, -2 bne sti, Szero, LOOP sub $t3, St3, Sti sw $t4, 0($t 3) Assume that there is no branch prediction and the branch condition is evaluated in the ID stage, the initial data stored in register Sts is 0x00000014. The initial data stored in memory is as follows: Memoso address Data 0x0000 0001 UX UUUU U004 UUUUUUUU2 UXUUUU OUV8 UXUD00000 (a) [6 pts) Consider inserting minimum number of NOP instructions into the above MIPS code to resolve hazards. You can use "NOP" to represent a NOP instruction. Show your new MIPS code sequence according to the two following cases: (1) Assume there is not any forwarding unit and path. (2) Assume there are full forwarding units and paths. (b) [8 pts] Complete the pipeline execution diagram of the new code sequence for the first 17 cycles and indicate the data forwarding. Please indicate the forwarding using the format (cycle number](pipeline register name) [cycle number](pipeline stage}, e.g. 9EX/MEM-9EX means that the data is forwarded from the EX/MEM pipeline register at cycle 9 to the EX stage at cycle 9. The execution of the first instruction has been given as an example. You do not need to show the execution of NOP instructions. Pipeline execution diagram: 4 5 9 10 11 12 13 14 15 16 17 Instruction ha Sil. 12:50) Forwarding