Question: 4. Suppose a pipelined MIPS processor has no branch delay slot, the branch and jump decision are made in Decode stage. The forwarding units in

4. Suppose a pipelined MIPS processor has no branch delay slot, the branch and jump decision are made in Decode stage. The forwarding units in Decode stage and Execute stage with inputs from Memory stage and WriteBack stage. How many cycles are required for this processor to complete all of the instructions for the following program? How many cycles are stalled? What is the average CPI of the processor on this program? (Total 10 points, the number of total cycles:3 points, the number of total instructions:3 points, the stalled cycles:2 points, the average CP1:2 points) addi Ss0, SO. 8 while: beqSs0, so done addi $50, S50,- j while done: sill s0.0.0

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