4.6 We wish to design a shift-left circuit manually. The inputs include a, which is an 8-bit signal to be shifted, and ctrl, which is a 3-bit signal specifying the amount to be shifted. Both are with the std_logic_vector data type. The output y is an 8-bit signal with the std_logic_vector data type. Use concurrent signal assignment statements to derive the circuit and draw the conceptual diagram. Problem 5: Problem 5.11 (page 123) from the textbook. Consider the shift-left circuit discussed in Problem 4.6 (Assignment 1). The inputs include a, which is an 8-bit signal to be shifted, and ctrl, which is a 3-bit signal specifying the amount to be shifted. Both are with the std_logic_vector data type. The output y is an 8-bit signal with the std_logic_vector data type. Use an if statement to derive the circuit and draw the conceptual diagram. 4.6 We wish to design a shift-left circuit manually. The inputs include a, which is an 8-bit signal to be shifted, and ctrl, which is a 3-bit signal specifying the amount to be shifted. Both are with the std_logic_vector data type. The output y is an 8-bit signal with the std_logic_vector data type. Use concurrent signal assignment statements to derive the circuit and draw the conceptual diagram. Problem 5: Problem 5.11 (page 123) from the textbook. Consider the shift-left circuit discussed in Problem 4.6 (Assignment 1). The inputs include a, which is an 8-bit signal to be shifted, and ctrl, which is a 3-bit signal specifying the amount to be shifted. Both are with the std_logic_vector data type. The output y is an 8-bit signal with the std_logic_vector data type. Use an if statement to derive the circuit and draw the conceptual diagram