4.7 Problems in this exercise assume that the logic blocks used to implement a processors datapath have the following latencies:

I-Mem/ D-Mem	Register File	Mux	ALU	Adder	Single gate	Register Read	Register Setup	Sign extend	Control
250ps	150ps	25ps	200ps	150ps	5ps	30ps	20ps	50ps	50ps

4.7.1 [20] <4.4> Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in Figure 2.20. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR.

4.7.2 [5] <4.4> What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)?

4.7.3 [10] <4.4> What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.)

4.7.4 [10] <4.4> What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.)

4.7.5 [5] <4.4> What is the latency of CBZ?

4.7.6 [5] <4.4> What is the latency of B?

4.7.7 [5] <4.4> What is the latency of an I-type instruction?

4.7.8 [5] <4.4> What is the minimum clock period for this CPU?