6. Problems in this exercise assume that the logic blocks used to implement a processor's datapath have the following latencies: B 30 ps I-Mem/Register Single Register Sign D-Mem File Mux ALU Adder gate Read extend Control 250 ps 150 ps 25 ps 200 ps 150 ps 5ps 50ps 50ps Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. (a) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (b) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (c) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of B? (e)What is the minimum clock period for this CPU