Problems in this exercise assume that the logic blocks used to implement a

processor$$s datapath have the following latencies:

I$-$Mem $/$

D$-$Mem

Register

File Mux ALU Adder

Single

gate

Register

Read

Register

Setup

Sign

extend Control

$250$ps $150$ps $25$ps $200$ps $150$ps $5$ps $30$ps $20$ps $50$ps $50$ps

$$Register read$$ is the time needed after the rising clock edge for the new register

value to appear on the output. This value applies to the PC only. $$Register setup$$ is

the amount of time a register$$s data input must be stable before the rising edge of

the clock. This value applies to both the PC and Register File.