$(50$ Pts$)$ Design a VHIDL model to implement the behavior of the function $F={}_{A,B,C,D}(4,6,13).$

a$.$ Draw a truth table for the function $F.$

b$.$ Use a process and an if$/$then statement. Use std logic and std logic vector for your signals.

c$.$ Declare the entity to match the block diagram below. Use the entity name

d$.$ Design a VHDL test bench to verify the function operation.

i$.$ Your test bench should drive in each input code for the vector ABCD in the order they appear in

ii$.$ Have your test bench change the input pattern every $100$ ns using wait for statement within your

stimulus process.

iii. Name your test bench file HW$9\_$TB

e$.$ Submit a screenshot showing the simulation results and all the combinations of the vector ABCD.

f$.$ Submit your VHDL your source and Test Bench files.