$5.(20\text{'})$ Sequential Circuit Design: The State Transition Graph $($STG$)$ of a sequence detector

$($Mealy machine$)$ is shown in Figure $2.$ It takes one$-$bit input $x,$ and set output $Z=1$ whenever the

input pattern sequence of $"1101"$ or $"1110"$ is detected, otherwise output $Z=0.$ Overlapping

sequences are allowed.

$.$ Assume $3D$ flip$-$flops $($rising$-$edge triggered$)$ are used to represent all the states, and the

following state assignments are used:

$S0=Q_2{Q}_1{Q}_0=000$;$,S1=Q_2{Q}_1{Q}_0=001$;$,S2=Q_2{Q}_1{Q}_0=010$;

$S3=Q_2{Q}_1{Q}_0=100,S4=Q_2{Q}_1{Q}_0=101.$

Construct the binary state transition table with excitation table based on $D$ flip$-$flops.

$.$ Based on binary state transition table, extract Karnaugh maps for each bit of the next states and

output $($i$.$e$.Q_2^{\text{'}}(D_2),Q_1\text{'}(=D_1),Q_0^{\text{'}}(=D_0)$ of flip$-$flop inputs and $Z)$ as functions of current states

and inputs $(Q_2,Q_1,Q_0,x).$ Derive the most simplified Boolean equations for $D_2,D_1,D_0$ and $Z=?$

$.$ Based on the simplified Boolean equations you found, implement the complete sequence

detector with logic gates and D flip$-$flops.

Figure $2.$ State Transition Graph $($STG$)$ of a sequence detector $($Mealy machine$)$