$[5]<2\mathrm{.}2,2\mathrm{.}3>$ Translate the following C code to MIPS. Assume that the variables f$,$ g$,$ h$,$ i$,$ and j are assigned to registers $s$0,$ $s$1,$ $s$2,$ $s$3,$and $s$4,$ respectively. Assume that the base address of the arrays A and B are in registers $s$6$ and $s$7,$ respectively. Assume that the elements of the arrays A and B are $8-$byte words:

B$[8]=$ A$[$i$]+$ A$[$j$]$:The code and interpretation on the website are as follows. However, if the array elements are eight bytes in size, shouldn't the shift left instruction be like this: sll $t$0,$ $s$3,3?$ I believe the $2$ here should be replaced with $3$ because shifting left by three positions is equivalent to multiplying by eight.# Perform shift logical left operation for register s$3$ by $2$ # Place the result in register t$0$

sll $t$0,$ $s$3,2$

# Perform addition operation t$0$ with s$6$

# Place the result in register t$0$

add $t$0,$ $t$0,$ $s$6$

#Perform load word function in the register t$0$

# With the location $0$

lw $t$0,0($$t$0)$

# Perform shift logical left operation for register s$4$ by $2$ # Place the result in register t$1$

sll $t$1,$ $s$4,2$

# Perform addition operation t$1$ with s$6$

# Place the result in register t$1$

add $t$1,$ $t$1,$ $s$6$

#Perform load word function in the register t$1$

# With the location $0$

lw $t$1,0($$t$1)$

# Perform addition operation t$0$ with s$1$

# Place the result in register t$0$

add $t$0,$$t$0,$$t$1$

# Perform store word function with the register s$7$ and t$0$

sw $t$0,32($$s$7)$