5. (22 points) Choose appropriate control signals and standard components, and design a datapath for a digital system whose registers PC, R1 and R2 have the following RTL operations, all of which should be synchronous (with a common clock). Data and Address are inputs to this datapath circuit. Each of the RTLs must be done in one clock cycle. Therefore, there cannot be a common bus as a constraint. Register PC Register R1 Register R2 PC 40 R1 R1 R2 R1 PC Address R1 Data PC PC+1 R1 R1 + R2 R1 R1 - R2 The n-bit registers should all have a 1-bit synchronous active high enable signal. Available components are multiplexers of any size, standard basic gates, adder-subtractor unit with a control signal Add/Sub (O for addition and 1 for subtraction), a counter with parallel load for PC, and parallel-load registers for R1 and R2. B B A Add/Sub Adder/Subtractor Sum Draw the datapath circuit using standard symbols. b. Fill in the corresponding control signals and their values for the each RTL below Register PC Control signals and their values PC Address PC PC+1 R1 R1' R1 R1 - R2 R2 R1