$5\mathrm{.}5$ For a direct$-$mapped cache design with a $32-$bit address, the following bits of the address are used to access the cache.

Tag Index Offset

$31109540$

$5\mathrm{.}5\mathrm{.}1[5]<5\mathrm{.}3>$ What is the cache block size $($in words$)?$

$5\mathrm{.}5\mathrm{.}2[5]<5\mathrm{.}3>$ How many entries does the cache have?

$5\mathrm{.}5\mathrm{.}3[5]<5\mathrm{.}3>$ What is the ratio between total bits required for such a cache implementation over the data storage bits?

Beginning from power on$,$ the following byte$-$addressed cache references are recorded.

Address

Hex $00041084$ E$8$ A$04001$E $8$C C$1$C B$4884$ Dec $041613223216010243014031001802180$

$5\mathrm{.}5\mathrm{.}4[20]<5\mathrm{.}3>$ For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

$5\mathrm{.}5\mathrm{.}5[10]<5\mathrm{.}3>$ What is the hit ratio?

$5\mathrm{.}5\mathrm{.}6[20]<5\mathrm{.}3>$ List the final state of the cache, with each valid entry represented as a record of $.$