for a direct mapped cache design with a 64-bit address the following bits of the address are used to access the cahe. Need help with 5.5.4 and 5.5.6

l why and tu the cache. If it is not possible, explain WI d address ocks. Also ly empty address rd blocks direct-mapped cache design with a 64-bit address, the following bits of or a ddress are used to access the cache. Index Offset Tag 9-5 4-0 63-10 ssumin 5,5.1 5 What is the cache block size (in words)? 5.5.2 (51 How many blocks does the cache have? 55.3 [5] What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are e given total of recorded Address Hex 00 04 10 84 E8 A0 400 1E8C C1C B4 884 Dec 0 4 16 132 232 160 1024 30 140 3100 180 2180 5.5.4 [20] For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). 5.5.5 [5]S53> What is the hit ratio? 5.5.6 [5] List the final state of the cache, with each valid entry represented as a record of . For example, tains M to how it as 32 rite allocation nolicies, and t a