$5\mathrm{.}5$ For a direct$-$mapped cache design with a $32-$bit address, the following bits of

the address are used to access the cache.

What is the cache block size $($in words$)?$

$5\mathrm{.}5\mathrm{.}2[5]$$$5\mathrm{.}3>$ How many blocks does the cache have?

$5\mathrm{.}5\mathrm{.}3[5]$$$5\mathrm{.}3>$ What is the ratio between total bits required for such a cache

implementation over the data storage bits?

Beginning from power on$,$ the following byte$-$addressed cache references are

recorded.

$5\mathrm{.}5\mathrm{.}4[20]$$$5\mathrm{.}3>$ For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether

it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

$5\mathrm{.}5\mathrm{.}5[5]$$$5\mathrm{.}3>$ What is the hit ratio?

$5\mathrm{.}5\mathrm{.}6[5]$$$5\mathrm{.}3>$ List the final state of the cache, with each valid entry represented

as a record of $($:$0,3,$Mem$[0xC00]-$Mem$[0xC1F]$:$)$