5. Assume the following 8-bit address sequence generated by the processor: Time Access10001100 Index Block inset- The cache uses 4 bytes per block and it can hold a total of 8 blocks. Assume a 2-way set associative cache design that uses the LRU algorithm and that the cache is initially empty a. Determine all fields in the address. b. Fill in the table above c. Mark Hit/Miss information for each access d. Mark if an access is replacing useful content in the cache. Use LRU e. Show content of the cache at the end