5. Assume the following 8-bit address sequence generated by the processor: 2 10110000 10111100 Time 1...

 

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5. Assume the following 8-bit address sequence generated by the processor: 2 10110000 10111100 Time 1 Access Tag 10001100 Set entry/index Block in Set 3 5 6 7 10001100 10011100 11101000 11111100 11101000 The cache uses 4 bytes per block and it can hold a total of 8 blocks. Assume a 2-way set associative cache design that uses the LRU algorithm and that the cache is initially empty. a. Determine all fields in the address. b. Fill in the table above c. Mark Hit/Miss information for each access. d. Mark if an access is replacing useful content in the cache. Use LRU. e. Show content of the cache at the end. 5. Assume the following 8-bit address sequence generated by the processor: 2 10110000 10111100 Time 1 Access Tag 10001100 Set entry/index Block in Set 3 5 6 7 10001100 10011100 11101000 11111100 11101000 The cache uses 4 bytes per block and it can hold a total of 8 blocks. Assume a 2-way set associative cache design that uses the LRU algorithm and that the cache is initially empty. a. Determine all fields in the address. b. Fill in the table above c. Mark Hit/Miss information for each access. d. Mark if an access is replacing useful content in the cache. Use LRU. e. Show content of the cache at the end.