5. Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no pipeline processing, assuming the instruction cycle below: . a one clock cycle fetclh a two clock cycle decode a two clock cycle execute and a 40 instruction sequence Show your work. No pipelining would require clock cycles: Scalar pipeline would require lock yles: Superscalar pipeline with two parallel units would require clock cycles