. Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle shown below:

a one clock cycle fetch

a one clock cycle decode

a two clock cycle execute

and a 80 instruction sequence:

Show your work. Be sure to factor in the cycles necessary for each instruction to execute.

a) No pipelining would require _____ clock cycles:

b). A scalar pipeline would require _____ clock cycles:

c) A superscalar pipeline with two parallel units would require ______ clock cycles