5) Given a processor with three stages with the following circuit delay: Fetch (75ns), Decode (100ns), Execute (125ns). What is the cycle time for a 3 stage pipeline? [Q5-3stage] What is the cycle time if this same functionality were implemented as a single stage pipeline (doing fetch, decode, and execute)? [Q5-1stage] For the follow code, what is the speedup of the 3 stage pipeline over the single stage pipeline? speedup percentage is defined as (old-new)/old, where in this example the 3 -stage pipeline is the new, and the single stage pipeline is the old. Enter up to 3 decimal places. [Q5-speedup] add 1,2,3 xori 4,5,0FFF and 6,x7,8 sili x9,10,3