Question: 5. Write the VHDL process for a JK flip-flop that only has an asynchronous clear and is positive-edge triggered. Use IF statements instead of a

5. Write the VHDL process for a JK flip-flop that only has an asynchronous clear and is positive-edge triggered. Use IF statements instead of a case statement. ENTITY prob2 IS PORT( clk, j, k, clear IN std_logic BUFFER std_logic) END prob2; ARCHITECTURE arc of prob2 IS BEGIN PROCESS (clk, clear) BEGINenter your process code here

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