$6-)(20$ points$)$ You've joined a hot new internet startup to build wrist watches with a built$-$in pager and

Web browser. It uses an embedded processor with a multilevel cache scheme depicted in Figure$-3.$

The processor includes a small on$-$chip cache in addition to a large off$-$chip second$-$level cache.

$($Yes$,$ the watch weighs $3$ pounds, but you should see it surft$)$

Assume that the processor uses $32-$bit physical addresses but accesses data only on word

boundaries. The caches have the characteristics given in Table$-1.$ The DRAM has an access time

of $t_{13}$ and a size of $512MB$

Table$-1$: Memory characteristics

a$.)$ For a given word in memory, what is the total number of locations in which it might be found in

the on$-$chip cache and in the second$-$level cache?

b$-)$ What is the size, in bits, of each tag for the on$-$chip cache and the second level cache?

c$.)$ Give an expression for the average memory read access time. The caches are apcessed in

sequence.

d$-)$ Measurements show that, for a particular problem of interest, the on$-$chip cache hit rate is $85\%$

and the second$-$level cache hit rate is $90\%.$ However, when the on$-$chip cache is disabled, the

second$-$level cache hit rate shoots up to $98\mathrm{.}5\%.$ Give a brief explanation of this behavior.