(6 points) A RISC processor executes the following code. There are data dependencies. A source operand cannot be used until it has been written. 13. LDR r2, [r4] MOV r3, r5 STR r6, [r2] Assuming a five-stage pipeline (fetch (IF), operand fetch (OF), execute (E), memory access (M), and register write (W)), how many extra cycles are required to ensure that the correct value of r2 is available for the STR instruction? 12 34 5 67 8 910 11 LDR r2, [r4] MOV r3, r5 STR r6, [r2] I F