Question: 6. Rewrite the following code to force the synthesis tools to share hardware resources. Draw the logic circuit synthesized from the codes before and after

6. Rewrite the following code to force the synthesis tools to

6. Rewrite the following code to force the synthesis tools to share hardware resources. Draw the logic circuit synthesized from the codes before and after applying the resource sharing. signal cntrl : std_logic; signal cntrl, a, b, c, d, e, f, z, temp_1, temp_2: std_logic_vector (7 downto 0); begin process (a, b, c, d, e, f, cntrl) begin if (cntrl) then temp_1

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