Rewrite the following code to force the synthesis tools to share hardware resources. Draw the logic circuit synthesized from the codes before and after applying the resource sharing. (15 points)

signal cntrl : std_logic;

signal a, b, c, d, e, f, z, temp_1, temp_2: std_logic_vector(7 downto 0);

begin

process (a, b, c, d, e, f, cntrl)

begin

if (cntrl = 1) then

temp_1 <= a + b;

z <= temp_1 + c;

else

temp_2 <= d + e;

z <= temp_2 + f;

end if;

end process;