6. Rewrite the following code to force the synthesis tools to share hardware resources. Draw the logic circuit synthesized from the codes before and after applying the resource sharing. signal cntrl ! std_logic; signal cntrl, a, b, c, d, e, f, z, temp_1, temp_2: std_logic_vector (7 downto 0); begin process (a, b, c, d, e, f, cntrl) begin if (cntrl) then else end if; end process; temp_1