6 The pipelined datapath of a MIPS processor can generally be broken down into 5 steps: 1. Hardware to support an instruction fetch 2. Hardware to support an instruction decode (i.e. a register file read) 3. Hardware to support instruction execution (i.e. the ALU) 4. Hardware to support a memory load or store 5. Hardware to support the write back of the ALU operation back to the register file Assume that each of the above steps takes the amount of time specified in Table Q6. Fetch 305 PS Decode 275 ps Execute 280 ps Memory 305 ps Write Back 250 ps Table Q6 Step execution times (2) (a) Given the times for the datapath stages listed above, what would the (2) minimum clock period be for the entire datapath? (b) In a pipelined datapath, assuming no hazards or stalls, how long will it take to (6) execute 1 instruction at such a clock rate? (c) Assuming that N instructions are executed, and all N instructions are add instructions, what is the speedup of a pipelined implementation when compared to a multi-cycle implementation? Your answer should be an expression that is a function of N