The multi-cycle and pipelined data paths that we have discussed in class have generally been broken down into 5 steps:

a. Hardware to support an instruction fetch

b. Hardware to support an instruction decode (i.e. a register file read)

c. Hardware to support instruction execution (i.e. the ALU)

d. Hardware to support a memory load or store

e. Hardware to support the write back of the ALU operation back to the register file

Assume that each of the above steps takes the amount of time specified in the table below.

Fetch 305 ps

Decode 275 ps

Execute 280 ps

Memory 305 ps

Write Back 250 ps

Calculate:

i. the clock period and the clock rate for the entire datapath?

ii. In a pipelined datapath, assuming no hazards or stalls, how many seconds will it take to execute 1 instruction?

iii. Assuming that N instructions are executed, and all N instructions are add instructions, what is the speedup of a pipelined implementation when compared to a multi-cycle implementation? Your answer should be an expression that is a function of N.

Consider Question 7 (above) to answer this question. Assume you break up the memory stage into 2 stages instead of 1 to improve throughput in a pipelined datapath. Thus, the pipeline stages are now:

F, D, EX, M1, M2, WB

Show how the instructions below would progress though this 6 stage pipeline. Like before, full forwarding hardware is available.