7) Given a 32-bit Harvard CPU, 256MB of data memory cache, and 64-bit cache entries:

a. How many cache entries are present?

b. How many bits of the address are dedicated to indexing into the cache?

c. How many bits of a cache entry are dedicated to the Key?

d. How many bits of a cache entry are used to hold the value?

e. How many bits are available for status information?

8) If the cache of question 7 is expanded to a 4-way associative cache (a total of 1GB):

a. How would you expect the change to affect the data memory hit rate?

b. How would you expect the change to affect the instruction fetch rate?

c. How would you expect the change to affect the speed of ALU operations?

d. How would you expect the change to affect access to peripheral devices?