7) Given basic MIPS five stage pipeline, with data forwarding, and the following instruction sets [20 pts, 10 pts each] instruction set #1 L1: lw $1,40($6) beq $2, $3, L2 add $1, $6, $4 L2: beq 1, $2, Ll sw $2, 20(*4) and $1, s1, $4 taken t not taken instruction set #2: add $1, $5, $3 Ll: sw $1, 0 ($2) add $2, $2,$3 beq $2, $4, LI add $5, $5, $1 sw $1, 8($2) not taken a) Assuming no delayed branches and that branches execute in the EX stage, draw the pipeline execution diagram for each set of code. b) Assuming there are delayed branches, that branches execute in the EX stage, and the instruction following the conditional branch is a safe instruction (i.e., allowed in the delay slot), draw the pipeline execution diagram for this code 7) Given basic MIPS five stage pipeline, with data forwarding, and the following instruction sets [20 pts, 10 pts each] instruction set #1 L1: lw $1,40($6) beq $2, $3, L2 add $1, $6, $4 L2: beq 1, $2, Ll sw $2, 20(*4) and $1, s1, $4 taken t not taken instruction set #2: add $1, $5, $3 Ll: sw $1, 0 ($2) add $2, $2,$3 beq $2, $4, LI add $5, $5, $1 sw $1, 8($2) not taken a) Assuming no delayed branches and that branches execute in the EX stage, draw the pipeline execution diagram for each set of code. b) Assuming there are delayed branches, that branches execute in the EX stage, and the instruction following the conditional branch is a safe instruction (i.e., allowed in the delay slot), draw the pipeline execution diagram for this code