$8.$ a$)(5)$ Does the single cycle data path correspond to a Princeton $($i$.$e$.,$ von Neumann$)$

architecture or does it correspond to a Harvard architecture? Explain your answer.

b$)(5)$ Does the single cycle data path compute a branch target address when the instruction

or $$4,$ $$3,$ $$2$ is executed? Explain your answer.

c$)(5)$ Explain why the single cycle data path must contain an ALU as well as two separate

adders.