$8-$bit Comparison Operations

You should build your own comparator that check the operands bit$-$by$-$bit, and not rely on builtin operators in Verilog, or you can subtract the numbers and decide, but be careful with overflow cases.

$\backslash$table$[[$OP#$,$Control Signals C$,$Operation$],[5,0110,$Minimum of A and B$],[6,0111,$Maximum of A and B$]]$

$8-$Bit Arithmetic and Logic Unit $($ALU$)$ Design

We would like to design an $8-$bit arithmetic and logic unit $($ALU$)$ that takes two inputs A and $B($two$\text{'}$s complement numbers$)$ each of size $8$ bits and that performs the following operations depending on the values of a control signal C $(4$ bits$).$

Arithmetic Operations

Addition and subtraction are supposed to be done for two's complement numbers.

You should only build a Two's complement adder and use it for all operations $($Operations #$1,$ #$2,$#$3,$#$4.$

The result of these operations, Result, is an $8-$bit vector.

Also, add a carry out signal, Cout.

$\backslash$table$[[$OP#$,$Control Signals C$,$Operation$],[1,0001,$A plus B$],[2,0010,$Increment A by $1],[3,0011,$A minus B$],[4,0100,$Decrement A by $1]]$

$8-$bit Comparison Operations

You should build your ownrcomparator that check the operands bit$-$by$-$bit, and not rely on builtin operators in Verilog, or you can subtract the numbers and decide, but be careful with overflow cases.

$\backslash$table$[[$OP#$,$Control Signals C$,$Operation$],[5,0110,$Minimum of A and

B$],[6,0111,$Maximum of A and B$]$

Testing:

You should implement a testbench that tests the circuit as follows:

For operations #$1$ to #$6$ use the following numbers:

A$=0$ B$=-2$

A$=50$ B$=50$

A$=50$ B$=75$

A$=-50$ B$=-75$

A$=100$ B$=-100$