8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 MEM WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: IF ID EX IF ID EX MEM WB ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2