8. You are building a computer with a hierarchical memory system that oonsists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor discussed in class running at 1 GHz 1 (a) Suppose the instruction cache is perfect (i.e. always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then rsumes normal operation. Taking cache misses into account, what is the average memory access? b) How many clock cycles per instruction (CPI) on average are required for load and store word instructions considering the non-ideal memory system? (c) Consider the benchmark application that has 25% loads 10% stores 11% branches, 2% Jumps, and 52% data-processing or R-type instructions. Taking the non-ideal memory system into acoount, what is the average CPI for this benchinark? (d) Now suppose that the instruction cache is a so non-ideal and has a 7% miss rate. What is the average CPI for the benchmark in part (c)? Take into account both instruction and data cache misses 9. Let's try the previous problem again but with worst-case performance metrics. (a) The instruction cache is perfect (i.e. always hits) but the data cache has a 15% miss rate. On a cache miss, the processor stalls for 200 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access ime? b) How many clock cycles per instruction (CPI) on average are required for load and store word instructions considering the non-ideal memory system? (c) Consider the benchmark application again from the previous question assuming that it has 25% loads 10% stores. 11% branches. 2 urnps, and 52% data processing or R-type instructions. Taking the non-ideal memory system into account. what is the average CPI for this benchmark? (b) Now suppose that the instruction cache is also non-ideal and has a 10% miss rate. What is the average CPI for the benchmark in part (c)? Take into account both instruction and data cache misses