You are building a computer with a hierarchical memory system that consists of separate

instruction and data caches followed by main memory. You are using a RISC$-$V multicycle

processor running at $5GHz.$

$($i$)$ The instruction cache is perfect $($i$.$e$.,$ always hits$)$ but the data cache has a $15\%$ miss

rate. On a cache miss, the processor stalls for $200$ns to access main memory, then

resumes normal operation. Taking cache misses into account, what is the average

memory access time?

$($ii$)$ How many clock cycles per instruction $($CPI$)$ on average are required for loa$5$d and

store word instructions considering the non$-$ideal memory system?

$($iii$)$ Consider a benchmark application that has $25\%$ loads, $10\%$ stores, $11\%$ branches, $2\%$

jumps, and $52\%$ R$-$type instructions. Taking the nonideal memory system into account,

what is the average CPI for this benchmark?

$($iv$)$ Suppose that the instruction cache is also nonideal and has a $10\%$ miss rate. What is

the average CPI for the benchmark in part $($c$)?$ Take into account both instruction and

data cache misses