Question: 9.4 Realize a full adder using a 3-to-8 line decoder (as in Figure 9-13) and (a) two OR gates. (b) two NOR gates. Analyze the

9.4 Realize a full adder using a 3-to-8 line decoder (as

9.4 Realize a full adder using a 3-to-8 line decoder (as in Figure 9-13) and (a) two OR gates. (b) two NOR gates. Analyze the following circuit and draw a truth table giving the value of F for cach of the 16 possible select input combinations of A,B,C,D C D Note that the value of F can be expressed in term of 0,, or N.Z. The Decoder outputs to the active enable lines of Mux that has 2 selects input C and D. C D MUX DCD C D YMUX

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