A $16-$bit computer featuring a streamlined memory hierarchy. This

hierarchy encompasses a solitary cache and an unbounded backing memory. The cache operates on a $2-$way set$-$associative model, with cache lines spanning $4$ bytes and a total capacity of $32$ bytes. Consider the ensuing sequence of memory word addresses:

$8,11,9,7,15,0,22,2,6,3$

$($a$)$ Ascertain the set index and block offset for each address in the provided sequence, representing them in binary notation. Incorporate the byte offset as an integral part of the block offset. Assuming an initially empty cache, evaluate whether each reference in the

address sequence yields a cache hit or a cache miss.

In the event of a cache miss, identify the specific type of cache miss$-$whether it is cold, conflict, or capacity. Utilize the table below to facilitate your responses:

$($b$)$ Create a table with the relevant data for each set and line after considering the memory addresses in the provided sequence. Include the necessary information about the stored data

in each cache line.