Consider a 16-bit computer with a simplified memory hierarchy. This hierarchy contains a single cache and an unbounded backing memory. The cache is 2- way set associative, 4-byte cache lines, and a capacity of 32 bytes. Consider also the following sequence of memory word addresses.

8, 3, 9, 7, 15, 20, 22, 2, 6, 0

(a) Determine, in binary notation, the set index and block offset for each address in the above sequence. Include the byte offset as part of the block offset. Assume the cache is initially empty. During the sequence of address accesses above, determine if each reference results in a cache hit or a cache miss. If the reference results in a cache miss, which type of cache miss occurs (cold, conflict, or capacity). Use the below table to help answer this question.

(b) Create a table which resembles this caches configuration. Fill that table such that it corresponds to the caches contents after all addresses in the above sequence have been referenced.

\begin{tabular}{|r|l|l|l|l|} \hline Address & Index & Block Offset & Hit or Miss & Type of Miss \\ \hline 8 & & & & \\ \hline 3 & & & & \\ \hline 9 & & & & \\ \hline 7 & & & & \\ \hline 15 & & & & \\ \hline 20 & & & & \\ \hline 22 & & & & \\ \hline 2 & & & & \\ \hline 6 & & & & \\ \hline 0 & & & & \\ \hline \end{tabular}