a) (10) Explain how an I-type load instruction would execute in this pipelined implementation. Show clearly that the result is written back in the proper Destination Register.

(b) (10) Define data dependency hazards and explain why they may occur in this implementation.

(c) (5) Show that a memory write (store) instruction cannot cause a data dependency hazard.

(d) (5) Can a store instruction be part of a data dependency hazard? Explain your answer.

(e) (10) Considering R, I and J-type instructions, explain how to detect data dependency hazards for all possible instruction-type sequences.

PCSrc IDIEX WB EX F/ID Add result Branch left 2 ALUSrc Read .[E@a. 1 register 2 Write Read data 1 Read Zero structio Registers Read data 2 resultAddress Data data Write 6Sign 32 6 15-0 16 MemRead ao1 control Instruction ALUOp 15-11 PCSrc IDIEX WB EX F/ID Add result Branch left 2 ALUSrc Read .[E@a. 1 register 2 Write Read data 1 Read Zero structio Registers Read data 2 resultAddress Data data Write 6Sign 32 6 15-0 16 MemRead ao1 control Instruction ALUOp 15-11