Consider the pipelined implementation (without forwarding and/or stalling) of the MIPS microprocessor as given above.

(a) Explain how an I-type load instruction would execute in this pipelined implementation. Show clearly that the result is written back in the proper Destination Register.

(b) Define data dependency hazards and explain why they may occur in this implementation.

(c) Show that a memory write (store) instruction cannot cause a data dependency hazard.

(d) Can a store instruction be part of a data dependency hazard? Explain your answer.

(e) Considering R, I and J-type instructions, explain how to detect data dependency hazards for all possible instruction-type sequences.

PCSrc IDVEX EX/MEM Control EX FID Add Add Add Branch left 2 PCAddress isRead Read Zero Registers Read Read result Adress Write Write data Instruction 16 15-01 Sign ALU control MemRead ALUOp 15-111 RegDst